(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices and, more particularly, to a method of creating damascene patterns that are essentially stress free.
(2) Description of the Prior Art
One of the more important aspects of the formation of semiconductor devices is the interconnection of devices and device features, this aspect of semiconductor design has gained increased importance with the continued decrease in device feature sizes and device dimensions. Not only is device geometry an important parameter in the design of device interconnects, the materials that form these interconnects and the interfacing of these materials with adjoining layers are of equal importance.
Two widely used approaches in creating metal interconnects are the use of the damascene and the dual damascene structures. The application of the damascene process continues to gain wider acceptance, most notably in the process of copper metalization due to the difficulty of copper dry etch where the damascene plug penetrates deep in very small, sub-half micron, Ultra Large Scale Integrated (ULSI) devices. Recent applications have successfully used copper as a conducting metal line, most notably in the construction of CMOS 6-layer copper metal devices.
In the formation of a damascene structure, a metal plug is first formed in a surface; this surface in most instances is the surface of a semiconductor substrate. A layer of Intra Level Dielectric (ILD) is deposited (using for instance Plasma Enhanced CVD technology with SiO.sub.2 as a dielectric) over the surface into which trenches for metal lines are formed (using for instance Reactive Ion Etching technology).
The trenches overlay the metal plug and are filled with metal (using for instance either the CVD or a metal flow process). Planarization of this metal to the top surface of the layer of ILD completes the damascene structure. Some early damascene structures have been achieved using Reactive Ion Etching (RIE) for the process of planarization but Chemical Mechanical Planarization (CMP) is used exclusively today.
An extension of the damascene process is the dual damascene process whereby an insulating or dielectric material, such as silicon oxide, is patterned with several thousand openings for the conductive lines and vias, which are filled at the same time with metal. Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in-addition to forming the grooves of single damascene, conductive via openings also are formed. One of the dual damascene approaches uses a dielectric layer that is formed by three consecutive depositions whereby the central layer functions as an etch stop layer. This etch stop layer can be SiN, the top and bottom layer of this three layer configuration can be SiO.sub.2. This triple layer dielectric allows first forming the vias by resist patterning the vias and etching through the three layers of dielectric. The conductive pattern can then be formed in the top layer of dielectric whereby the central layer of SiN forms the stop layer for the etch of the conducting pattern. Another approach, still using the three-layer dielectric formed on the substrate surface, is to first form the pattern for the conducting lines in the top layer of the dielectric, whereby the SiN layer again serves as etch stop. The vias can then be formed by aligning the via pattern with the pattern of the conducting lines and patterning and etching the vias through the etch stop layer of SiN and the first layer of dielectric. Yet another approach is to deposit the three layer dielectric in two steps, first depositing the first layer of SiO.sub.2 and the etch stop layer of SiN. At this point the via pattern can be exposed and etched. The top layer of SiO.sub.2 dielectric is then deposited; the conducting lines are now patterned and etched. The SiN layer will stop the etching except where the via openings have already been etched.
Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating process steps.
In the formation of semiconductor integrated circuits, it is common practice to form interconnect metal line structures on a number of different levels within the structure and interconnecting the various levels of wiring with contact or via openings. The first or lowest level of interconnect wires is typically formed as a first step in the process after which a second or overlying level of interconnect wires is deposited over the first level. The first level of interconnect wires is typically in contact with active regions in a semiconductor substrate but is not limited to such contact. The first level of interconnect can for instance also be in contact with a conductor that leads to other devices that form part of a larger, multi-chip structure. The two levels of metal wires are connected by openings between the two layers that are filled with metal where the openings between the two layers are lined up with and match contact points in one or both of the levels of metal lines.
Previously used techniques to form multi-levels of wiring apply the technique of first forming the interconnect level metal in a first plane followed by forming the overlying level of interconnect wire in a second plane. This structure typically starts with the surface of a semiconductor substrate into which active devices have been created. These active devices can include bipolar transistors, MOSFET devices, doped regions that interconnect with other regions of the device while provisions may also have been provided to make interconnects with I/O terminals in the periphery of the device. The surface into which the pattern of interconnect lines of the first plane is formed may also be an insulation layer deposited over the surface of the substrate or a layer of oxide may first have been formed on the surface of the substrate. After the layer, into which the pattern of interconnecting wires has to be created, has been defined, the interconnecting pattern itself needs to be defined. This is done using conventional photolithographic techniques whereby the openings are made (in the layer) above the points that need to be contacted in the substrate. The openings, once created, may by lined with layers of material to enhance metal adhesion (to the sidewalls of the opening), the glue layer, or to prevent diffusion of materials into and from the substrate in subsequent processing steps, the barrier layer. For the barrier layer, a variety of materials can be used such as Ti/Tin:W (titanium/titanium nitride:tungsten), titanium-tungsten/titanium or titanium-tungsten nitride/titanium or titanium nitride or titanium nitride/titanium, silicon nitride (Si.sub.3 N.sub.4), tungsten, tantalum, niobium, molybdenum. The final phase in creating the first level of interconnect lines is to fill the created openings with metal, typically aluminum, tungsten or copper, dependent on the particular application and requirements and restrictions imposed by such parameters as line width, aspect ratio of the opening, required planarity of the surface of the deposited metal and others.
This process of line formation in overlying layers on metal can be repeated in essentially the same manner as just highlighted for the first layer of interconnecting wires. This process of forming sequential layers of interconnecting levels of wire is in many instances prone to problems and limitations. Copper has in recent times found more application in the use of metal wires due to its low resistivity, high electromigration resistance and stress voiding resistance. Copper however exhibits the disadvantage of high diffusivity in common insulating materials such as silicon dioxide and oxygen-containing polymers. This leads to, for instance, the diffusion of copper into polyimide during high temperature processing of the polyimide resulting in severe erosion of the copper and the polyimide due to the copper combining with oxygen in the polyimide. The erosion may result in loss of adhesion, delamination, voids, and ultimately a catastrophic failure of the component. The copper that is used in an interconnect may diffuse into the silicon dioxide layer causing the dielectric strength to become conductive and also decreasing the dielectric strength of the silicon dioxide layer. A copper diffusion barrier is therefore often required; silicon nitride is often applied as a diffusion barrier to copper. Silicon nitride however has a dielectric constant that is high compared to silicon dioxide thereby limiting the use of silicon nitride in encapsulating copper interconnect lines.
In addition, due to the fact that copper is very difficult to process by RIE, the CMP method may need to be used where copper is used as a wiring material. To polish copper at a high rate without scratching in accordance with the buried wiring formation, the copper etch rate must be raised by increasing the amount of the component responsible for copper etching contained in the polishing slurry. If the component is used in an increased amount, the etching will occur isotropically. Consequently, buried copper is etched away, causing dishing in the wiring. It is, when forming interconnect lines using copper, desirable to use methods that do not depend on patterning the copper lines using a chemical etching process since etching of copper is very difficult and is a process that is only recently being further investigated. The use of copper as a metal for interconnect wiring is further hindered by copper's susceptibility to oxidation. Conventional photoresist processing cannot be used when the copper is to be patterned into various wire shapes because the photoresist needs to be removed at the end of the process by heating it in a highly oxidized environment, such as an oxygen plasma, thereby converting it to an easily removed ash.
For a damascene structure where copper is used as the metal and Ta and/or Ta compounds are used for the barrier layer, the dishing of the surface of large trenches and the erosion that occurs on the surface of small structures is, after CMP of the copper surface, very severe due to the extreme difference in polishing rate between copper and Ta-based materials. Ta-based materials have a low chemical mechanical polishing rate due to their hard and chemically inert nature whereas copper has a high chemical mechanical polishing rate due to its soft nature. It is therefore clear that, where copper and Ta-based materials are polished in proximity to each other and as part of the same polishing process, the surfaces of these two material will be affected or polished in an unequal manner resulting in dishing and erosion of the polished copper surface.
The planarization of copper surfaces that use CMP techniques results in copper surfaces of excellent planarity. This excellent planarity however makes adherence by overlying layers, such as passivation layers that contain oxides and nitrides, very difficult and causes relatively large stress in these overlying layers. This poor adhesion and large stress causes the overlying layer to readily peel during thermal cycles of the substrate caused by the different coefficients of thermal expansion of the interfacing surfaces. The invention addresses this problem by teaching a method that eliminates the presence of relatively large, very flat surfaces during the formation of damascene interconnects. The stress that typically exists in overlying layers will be reduced thereby reducing peeling of overlying layers and removing a potential yield detractor.
FIG. 1 shows a cross section of a typical formation of interconnect metal lines. A stop layer 20 (typically of SiN) has been deposited over the surface 10, which is typically the surface of a monocrystalline silicon substrate. The stop layer functions as the etch stop for the etching of the layer 12 of IMD. A layer 12 of Intra Metal Dielectric (IMD) is deposited over the surface of stop layer 20. Layer 12 of IMD is preferably formed of plasma oxide or LPCVD oxide material and specifically has a thickness of between 5000 and 15000 angstrom and more preferably about 15000 angstrom.
The layer 12 of IMD is patterned whereby the IMD is removed from the regions within the layer of IMD where the metal 18 for the pattern of interconnect lines is to be deposited. Standard photolithography and RIE procedures, using CF.sub.4 /CHF.sub.3 as etchant gas, can be used to create the trenches for the metal pattern in the layer 12 of dielectric.
Before the metal 18 is deposited, a barrier layer 14 and seed layer 16 are frequently deposited over the surface of the patterned layer 12 of IMD and along the walls and over the bottom of the openings that been created in the layer 12 of IMD for the metal interconnect lines.
FIG. 2 shows a cross section of the prior art after the layer 18 of copper has been planarized essentially down to the surface of the layer 12 of IMD. The sidewalls and bottom of the metal pattern 18 of FIG. 2 is surrounded by the barrier layer 14 and the seed layer 16. The planarization of the layer of copper has resulted in a very smooth copper surface 25 that has excellent surface planarity. The smoothness of this surface 25 however results in the previously highlighted problems of lack of adhesion of overlying layers of passivation. It is this problem of the lack of adhesion between the copper surface 25 and the overlying passivation layer that the invention addresses.
FIG. 3 shows a cross section of the prior art where a passivation layer comprising layer 22, containing SiO.sub.x, and layer 24, containing Si.sub.x N.sub.y, have been deposited over the surface of the IMD and the surface of the copper pattern 18.
U.S. Pat. No. 5,916,823 (Lou et al.) and U.S. Pat. No. 5,753,967 (Lin) show a dual damascene processes with spacers.
U.S. Pat. No. 5,834,365 (Ming-Tsung et al.) shows a bond pad with dummy lines thereunder to improve adhesion. This is close to the invention's (second) embodiment
U.S. Pat. No. 5,554,418 (Ito et al.) and U.S. Pat. No. 5,821,174 (Hong et al.) and U.S. Pat. No. 5,943,599 (Yao et al.) show processes for forming a passivation layer over a line.
U.S. Pat. No. 5,494,853 (Lur) and U.S. Pat. No. 5,924,006 (Lur et al.) shows a process for forming metal lines under a passivation layer. However, this reference differs from the invention.